Clock tree synthesis with skew for memory devices
US6941533B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 21, 2002 |
| Grant date | Sep 6, 2005 |
| Priority date | — |
| Expiry date | Oct 9, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/396
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of synthesizing a clock tree for reducing peak power in an integrated circuit design includes partitioning a circuit design into a set of memory cells and a set of non-memory cells, partitioning the set of memory cells into segments, constructing a first clock tree having a first root vertex with a corresponding initial skew for each of the segments, constructing a second clock tree having a second root vertex with a corresponding initial skew for the set of non-memory cells, delay balancing the first root vertex and the second vertex clock tree, and inserting a clock buffer at a midpoint between the first root vertex and the second root vertex.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.