Efficiency of reconfigurable hardware
US6941539B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 31, 2002 |
| Grant date | Sep 6, 2005 |
| Priority date | — |
| Expiry date | Aug 22, 2023 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention includes a method of computing a function array in reconfigurable hardware that includes forming in the reconfigurable hardware a first delay queue and a second delay queue, inputting from a source array outside the reconfigurable hardware a first value into the first delay queue and a second value into the second delay queue, defining in the reconfigurable hardware a window array comprising a first cell and a second cell, inputting the first value from the first delay queue into the first cell and the second value from the second delay queue into the second cell, and calculating an output value for the function array based on the window array. The present invention also includes a method of loop stripmining and a method of calculating output values in a fused producer/consumer loop structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.