Three-dimensional integrated semiconductor devices
US6943067B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 30, 2002 |
| Grant date | Sep 13, 2005 |
| Priority date | — |
| Expiry date | Sep 30, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention describes a process for three-dimensional integration of semiconductor devices and a resulting device. The process combines low temperature wafer bonding methods with backside/substrate contact processing methods, preferably with silicon on insulator devices. The present invention utilizes, in an inventive fashion, low temperature bonding processes used for bonded silicon on insulator (SOI) wafer technology. This low temperature bonding technology is adopted for stacking several silicon layers on top of each other and building active transistors and other circuit elements in each one. The back-side/substrate contact processing methods allow the interconnection of the bonded SOI layers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.