Selective spacer layer deposition method for forming spacers with different widths
US6943077B2 · kind B2 · utility
11Cited by
30References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 7, 2003 |
| Grant date | Sep 13, 2005 |
| Priority date | — |
| Expiry date | Apr 7, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0147
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming spacers with different widths on a semiconductor substrate, includes the steps of disposing a first spacer layer over the substrate, defining the first spacer layer into a plurality of spacers of a first width, and disposing a second spacer layer selectively over the first spacer layer of a number of the spacers preselected for the second spacer layer, the predetermined number of the spacers with the second spacer layer each having a second width which is different from the first width.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.