Defect-free thin and planar film processing
US6943112B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 3, 2003 |
| Grant date | Sep 13, 2005 |
| Priority date | — |
| Expiry date | Mar 3, 2023 |
Classification
- Technology area (CPC C)Chemistry; Metallurgy
- CPC primaryC25D7/123
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The process of the present invention forms copper interconnects in a semiconductor wafer surface. During the process, initially, narrow and large features are provided in the top surface of the wafer, and then a primary copper layer is deposited by employing an electrochemical deposition process. The primary copper layer completely fills the features and forms a planar surface over the narrow feature and a non-planar surface over the large feature. By employing an electrochemical mechanical deposition process, a secondary copper layer is deposited onto the primary copper layer to form a planar copper layer over the narrow and large features. After this process step, the thickness of the planar copper layer is reduced using an electropolishing process.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.