Low leakage heterojunction vertical transistors and high performance devices thereof

US6943407B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Qiqing C. Ouyang · Yorktown Heights, US
• Jack O. Chu · Manhasset Hills, US

Key dates

• Filing date: Jun 17, 2003
• Grant date: Sep 13, 2005
• Expiry date: Jun 17, 2023

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D62/832

Abstract

A method for forming and the structure of a vertical channel of a field effect transistor, a field effect transistor and CMOS circuitry are described incorporating a drain, body and source region on a sidewall of a vertical single crystal semiconductor structure wherein a hetero-junction is formed between the source and body of the transistor, wherein the source region and channel are independently lattice strained with respect the body region and wherein the drain region contains a carbon doped region to prevent the diffusion of dopants (i.e., B and P) into the body. The invention reduces the problem of short channel effects such as drain induced barrier lowering and the leakage current from the source to drain regions via the hetero-junction and while independently permitting lattice strain in the channel region for increased mobility via choice of the semiconductor materials. The problem of scalability of the gate length below 100 nm is overcome by the heterojunction between the source and body regions.