Inventor · Yorktown Heights, NY, US

Qiqing C. Ouyang

84Patents
15h-index
77Co-inventors
87Inventor score

Filing activity: May 9, 2000 → Sep 24, 2020

Most-cited inventions

PatentTitleAreaCited byStatus
US6943407B2 Low leakage heterojunction vertical transistors and high performance devices thereof Electricity 436 Expired
US8895395B1 Reduced resistance SiGe FinFET devices and method of forming same Electricity 312 Active
US7309626B2 Quasi self-aligned source/drain FinFET process Electricity 130 Expired
US6319799A High mobility heterojunction transistor and method Electricity 129 Expired
US7057216B2 High mobility heterojunction complementary field effect transistors and methods thereof Electricity 127 Expired
US7205604B2 Ultra scalable high speed heterojunction vertical n-channel MISFETs and methods thereof Electricity 82 Expired
US7227205B2 Strained-silicon CMOS device and method Electricity 49 Expired
US7368358B2 Method for producing field effect device that includes epitaxially growing SiGe source/drain regions laterally from a silicon body Electricity 47 Active
US7705345B2 High performance strained silicon FinFETs device and method for forming same Electricity 46 Expired
US6927414B2 High speed lateral heterojunction MISFETs realized by 2-dimensional bandgap engineering and methods thereof Emerging Cross-Sectional Technologies 28 Expired
US7872303B2 FinFET with longitudinal stress in a channel Electricity 26 Active
US9643181B1 Integrated microfluidics system Physics 20 Active
US7510904B2 Structure for and method of fabricating a high-speed CMOS-compatible Ge-on-insulator photodetector Emerging Cross-Sectional Technologies 17 Active
US7294879B2 Vertical MOSFET with dual work function materials Electricity 16 Expired
US7968915B2 Dual stress memorization technique for CMOS application Electricity 15 Active
US8993406B1 FinFET device having a merged source drain region under contact areas and unmerged fins between contact areas, and a method of manufacturing same Electricity 14 Active
US7834399B2 Dual stress memorization technique for CMOS application Electricity 13 Active
US7375410B2 Ultra-thin SOI vertical bipolar transistors with an inversion collector on thin-buried oxide (BOX) for low substrate-bias operation and methods thereof Electricity 11 Expired
US7381655B2 Mandrel/trim alignment in SIT processing Electricity 11 Active
US9505611B1 Integration of electromechanical and CMOS devices in front-end-of-line using replacement metal gate process flow Performing Operations; Transporting 11 Active
US6855963B1 Ultra high-speed Si/SiGe modulation-doped field effect transistors on ultra thin SOI/SGOI substrate Electricity 11 Expired
US7525161B2 Strained MOS devices using source/drain epitaxy Electricity 11 Active
US7453113B2 Ultra scalable high speed heterojunction vertical n-channel MISFETs and methods thereof Electricity 10 Active
US7161220B2 High speed photodiode with a barrier layer for blocking or eliminating slow photonic carriers and method for forming same Electricity 9 Expired
US9443873B1 Structure and method for tensile and compressive strained silicon germanium with same germanium concentration by single epitaxy step Electricity 9 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.