Method, system and apparatus to detect defects in semiconductor devices
US6943569B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 12, 2002 |
| Grant date | Sep 13, 2005 |
| Priority date | — |
| Expiry date | Aug 11, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method and system to locate and detect voids in films that are involved in critical dimension (CD) structures and non-critical dimension structures in semiconductor devices are presented. One or more test structures (resolution devices) are formed on a semiconductor wafer. A scanning electron microscope is operated in voltage contrast mode to obtain a digital representation of the test structure. The voltage contrast image of the test structure is then analyzed with a system which automates the location, identification, and categorization of voids in the test structure. Additionally, the method is more sensitive to electrical marginalities caused by voids than other wafer electrical testing methods. The method is suitable inline monitoring during a manufacturing process by utilizing the automation of void identification, location, and categorization as a process monitoring parameter.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.