NRAM bit selectable two-device nanotube array
US6944054B2 · kind B2 · utility
44Cited by
22References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 26, 2004 |
| Grant date | Sep 13, 2005 |
| Priority date | — |
| Expiry date | Mar 26, 2024 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S977/943
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A non-volatile memory array includes a plurality of memory cells, each cell receiving a bit line, word line, and release line. Each memory cell includes a cell selection transistor and a restore transistor with first, second and third nodes. Each cell further includes an electromechanically deflectable switch, the position of which manifests the logical state of the cell. Each cell is bit selectable for read and write operations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.