Routability for memory devices
US6944694B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 11, 2001 |
| Grant date | Sep 13, 2005 |
| Priority date | — |
| Expiry date | Dec 27, 2022 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer system provides improved routability for memory modules. Chips are placed on the back side of the module directly behind the chips on the front side, and vias connects destination pins on the front side to the back side. Internal assignments are routed to the pins so as to be bilaterally symmetrical. These functions can include any of the pins used on the memory chip, including the address bus and the command bus. The bit positions of the internal assignments routed to pins connected together need not be identical. Where bit positions are coupled together, a remap multiplexer is used to perform rerouting of logical information onto different physical bus lines. The remap multiplexer may be implemented in the system BIOS, in the memory controller, or altematively on the memory module. Further, the rerouting may be accomplished through any combination of hardware or software.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.