RISC processor supporting one or more uninterruptible co-processors
US6944746B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 1, 2002 |
| Grant date | Sep 13, 2005 |
| Priority date | — |
| Expiry date | Oct 23, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N19/90
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A system and method for processing instructions in a computer system comprising a processor and a co-processor communicatively coupled to the processor. Instructions are processed in the processor in an instruction pipeline. In the instruction pipeline, instructions are processed sequentially by an instruction fetch stage, an instruction decode stage, an instruction execute stage, a memory access stage and a result write-back stage. If a co-processor instruction is received by the processor, the co-processor instruction is held in the core processor until the co-processor instruction reaches the memory access stage, at which time the co-processor instruction is transmitted to the co-processor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.