Integrated passive components and package with posts
US6946734B2 · kind B2 · utility
2Cited by
34References
7Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 20, 2004 |
| Grant date | Sep 20, 2005 |
| Priority date | — |
| Expiry date | Feb 20, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/30107
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for an electronic component package of a passive component using wafer level processing;is provided. Posts are formed on the active side of the substrate of an electronic component. A conductive layer leads the contact areas of the electronic component to the tops of the posts. The conductive layer on the top of the posts acting as leads, attaching to traces on a printed circuit board.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.