Circuit for calibrating a resistance
US6946849B1 · kind B1 · utility
11Cited by
2References
19Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jun 15, 2004 |
| Grant date | Sep 20, 2005 |
| Priority date | — |
| Expiry date | Jun 15, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2203/45702
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A circuit for calibrating a resistance between a first circuit node and a second circuit node is disclosed. The circuit comprises a reference resistor connected between first and second reference nodes; a first transistor having a first current-handling terminal connected to the first reference node, a second current-handling terminal, and a first control terminal; and a second transistor having a third current-handling terminal connected to the first circuit node, a fourth current-handling terminal connected to the second circuit node, and a second control terminal connected to the first control terminal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.