Phase-locked loop circuit, information processing apparatus, and information processing system
US6947514B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 26, 1998 |
| Grant date | Sep 20, 2005 |
| Priority date | — |
| Expiry date | Jun 26, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/113
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A phase locked loop (PLL) circuit is provided to operate in a broad band, including two separate loops one of which is for feed-back of an output from an oscillator to the same oscillator through its associative proportional control unit and the other of which is for feed-back of an output of an oscillator to the same oscillator via an integral control unit. The proportional control unit is arranged to control an output frequency of the oscillator and is operable to generate a control signal based on a difference between input and output signals. The integral control unit is arranged to control the phase of an output signal of the oscillator to thereby generate a control signal based on a phase difference between input and output signals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.