Method and apparatus having dynamically scalable clock domains for selectively interconnecting subsystems on a synchronous bus
US6948017B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 18, 2002 |
| Grant date | Sep 20, 2005 |
| Priority date | — |
| Expiry date | Oct 17, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/364
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one form, a method for communicating among subsystems coupled to a bus of a computer system on an integrated circuitry chip includes operating subsystems at independent clock frequencies when the subsystems are not communicating with one another on the bus. Selected pairs of the subsystems are operated at a shared clock frequency by selectively varying frequencies of clock signals to the subsystems, so that communication can occur at the shared clock frequency on the bus between the selected subsystems, but at different clock frequencies for respective different pairings of the subsystems, and so that the subsystems can operate at independent clock frequencies when not communicating with other ones of the subsystems. Communication among the subsystems is by a bus-based protocol, according to which when a subsystem is granted access to the bus the subsystem has exclusive use of the bus.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.