Method for depositing a metal layer on a semiconductor interconnect structure
US6949461B2 · kind B2 · utility
18Cited by
15References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 11, 2002 |
| Grant date | Sep 27, 2005 |
| Priority date | — |
| Expiry date | Dec 11, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76865
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Disclosed is a method for depositing a metal layer on an interconnect structure for a semiconductor wafer. In the method, a metal conductor is covered by a dielectric layer. The dielectric layer is patterned so as to expose the metal conductor. A liner layer is then deposited into the pattern. The liner layer is then argon sputter etched to remove the liner layer and expose the metal conductor. In the process of argon sputter etching, the liner layer is redeposited onto the sidewall of the pattern. Lastly, an additional layer is deposited into the pattern and covers the redeposited liner layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.