Memory cell transistor having different source/drain junction profiles connected to DC node and BC node and manufacturing method thereof
US6949783B2 · kind B2 · utility
2Cited by
10References
16Claims
0Family size
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Key dates
| Filing date | Sep 5, 2002 |
| Grant date | Sep 27, 2005 |
| Priority date | — |
| Expiry date | Sep 5, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/021
Abstract
A memory cell transistor of a DRAM device is provided. A gate stack pattern is formed on a semiconductor substrate. A DC node and a BC node are formed substantially under lateral sides of the gate stack pattern in the semiconductor substrate. The DC node and the BC node are being electrically connected to a bit line and a storage electrode of a capacitor respectively. A first source/drain junction region is formed under the DC node and a second source/drain junction region is formed under the BC node. The first source/drain junction region has a profile which is different from that of the second source/drain junction region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.