Bandwidth reduction for rendering using vertex data
US6950108B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 27, 2004 |
| Grant date | Sep 27, 2005 |
| Priority date | — |
| Expiry date | May 27, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06T15/005
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments of the present invention provide a split vertex buffer where the data for each vertex is split between parallel vertex buffers. The first buffer contains vertex X and Y data, while the second parallel buffer contains the remainder of the vertex data. Given the split vertex buffers, the hardware binning-engine is now permitted to read and cache only vertex screen X and Y data. Especially given a typically high level of temporal coherency between indexed vertex references, the reading and caching of large parcels of vertex screen-space X and Y leads to lower and highly efficient utilization of memory bandwidth for hardware binning input. Embodiments of the present invention thus reduce the hardware binning memory bandwidth requirements and improve memory utilization.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.