Cell data margin test with dummy cell
US6950353B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 1, 2005 |
| Grant date | Sep 27, 2005 |
| Priority date | — |
| Expiry date | Feb 1, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/1204
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory array includes a true bitline and a complementary bitline and a sense amplifier connected thereto; a row of normal cells with capacitors for data storage and bitline storage capacitors. A row of dummy cells with dummy cell capacitors is also provided. A clock provides wordline drive signals to the normal cells. When operating in the test mode, the clock provides at least one dummy wordline drive signal to the dummy cell switch in response to a testing signal for connecting the dummy cell capacitor to the bitline. A plurality of rows of dummy cells can be employed with various permutations of actuation thereof to provide various levels of capacitance connected to the bitlines in the test mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.