Synchronous memory device for preventing erroneous operation due to DQS ripple
US6950370B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 16, 2003 |
| Grant date | Sep 27, 2005 |
| Priority date | — |
| Expiry date | Dec 16, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/22
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A synchronous memory device, receiving a number of data in synchronization with a rising edge and a falling edge of a clock, includes a data strobe buffering unit, a data align latching unit and a DQS signal controlling unit. The data strobe buffering unit outputs a rising pulse and a falling pulse for detecting a rising edge and a falling edge of a DQS signal that sustains a high impedance state when there is no operation and is clocked while the data is inputted. The data align latching unit latches and aligns the data in synchronization with the rising pulse and the falling pulse. The DQS signal controlling unit controls the data strobe buffering unit to output the rising pulse and the falling pulse to the data align latching unit only when the DQS signal is clocked.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.