Correlation of electrical test data with physical defect data
US6950771B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 9, 2003 |
| Grant date | Sep 27, 2005 |
| Priority date | — |
| Expiry date | Mar 3, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/1806
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Method and apparatus are disclosed for analyzing defect data produced in testing a semiconductor chip from a logic design. In various embodiments, input for processing is a first inspection data set that identifies a first set of physical locations that are associated with defects detected during fabrication of the chip. Also input is a second test data set that includes one or more identifiers associated with failing circuitry in the chip. A second set of physical locations is determined from the one or more identifiers of failing circuitry, hierarchical relationships between blocks of the design, and placement information associated with the blocks. Each of the one or more identifiers is associated with at least one of the blocks. Correspondences are identified between physical locations in the first inspection data set and the second set of physical locations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.