Method of fabricating a random access memory device utilizing a vertically oriented select transistor
US6951789B2 · kind B2 · utility
7Cited by
14References
26Claims
0Family size
Assignee
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Key dates
| Filing date | Jun 29, 2004 |
| Grant date | Oct 4, 2005 |
| Priority date | — |
| Expiry date | Jun 29, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory structure has a vertically oriented access transistor with an annular gate region. A transistor is fabricated such that the channel of the transistor extends outward with respect to the surface of the substrate. An annular gate is fabricated around the vertical channel such that it partially or completely surrounds the channel. A buried annular bitline may also be implemented. After the vertically oriented transistor is fabricated with the annular gate, a storage device may be fabricated over the transistor to provide a memory cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.