Semiconductor device including band-engineered superlattice
US6952018B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 19, 2003 |
| Grant date | Oct 4, 2005 |
| Priority date | — |
| Expiry date | Dec 1, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
A semiconductor device includes a superlattice that, in turn, includes a plurality of stacked groups of layers. The device may also include regions for causing transport of charge carriers through the superlattice in a parallel direction relative to the stacked groups of layers. Each group of the superlattice may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and an energy band-modifying layer thereon. Moreover, the energy-band modifying layer may include at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. Accordingly, the superlattice may have a higher charge carrier mobility in the parallel direction than would otherwise be present.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.