Ferroelectric memory devices with expanded plate line and methods in fabricating the same
US6952028B2 · kind B2 · utility
6Cited by
9References
33Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 22, 2003 |
| Grant date | Oct 4, 2005 |
| Priority date | — |
| Expiry date | Jul 29, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76852
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A ferroelectric memory device includes a lower interlayer dielectric on a semiconductor substrate, a plurality of ferroelectric capacitors, and a plate line. The ferroelectric capacitors are on the lower interlayer dielectric. The plate line extends across and electrically connects to surfaces of at least two adjacent ones of the plurality of ferroelectric capacitors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.