Gate-clocked domino circuits with reduced leakage current
US6952118B2 · kind B2 · utility
9Cited by
8References
25Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 18, 2002 |
| Grant date | Oct 4, 2005 |
| Priority date | — |
| Expiry date | Jan 24, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/0963
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A gate-clocked domino circuit with reduced leakage current during an inactive state, where domino stages in the domino circuit have long channel length transistors in the pre-charge paths. During an inactive state, the domino stages are put in an evaluation state and are discharged.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.