Method for manufacturing shallow trench isolation in semiconductor device
US6953734B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 16, 2003 |
| Grant date | Oct 11, 2005 |
| Priority date | — |
| Expiry date | Dec 16, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76224
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The method for manufacturing an STI in a semiconductor device with an enhanced gap-fill property and leakage property is disclosed by introducing a nitridation process instead of forming a liner nitride. The method includes steps of: preparing a semiconductor substrate obtained by a predetermined process on which a pad oxide and a pad nitride are formed on predetermined locations thereof; forming an isolation trench with a predetermined depth in the semiconductor substrate; forming a wall oxide on the trench; forming a liner oxide on the wall oxide and an exposed surface of the pad nitride; carrying out a nitridation process for forming a nitrided oxide; forming an insulating layer over the resultant structure, wherein the isolation trench is filled with the insulating layer; and planarizing a top face of the insulating layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.