Semiconductor device having borderless logic array and flexible I/O
US6953956B2 · kind B2 · utility
462Cited by
24References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 18, 2002 |
| Grant date | Oct 11, 2005 |
| Priority date | — |
| Expiry date | Feb 23, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3011
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A novel method is presented to provide ASICs with drastically reduced NRE and with volume flexibility. The invention includes a method of fabricating an integrated circuit, including the steps of: providing a semiconductor substrate, forming a borderless logic array including a plurality of Area I/Os and also including the step of forming redistribution layer for redistribution at least some of the Area I/Os for the purpose of the device packaging. The fabrication may utilize Direct Write e-Beam for customization. The customization step may include fabricating various types of devices at different volume from the same wafer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.