Boosted potential generation circuit and control method
US6954386B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Feb 20, 2003 |
| Grant date | Oct 11, 2005 |
| Priority date | — |
| Expiry date | Aug 23, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C5/145
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A boosted potential generation circuit enables a high-speed operation and even miniaturization in a semiconductor memory even if external power supply voltage is reduced in the semiconductor memory. In the boosted potential generation circuit provided with a capacitor MOS transistor and a transfer MOS transistor and used for a DRAM including memory cells, a gate insulating film of the capacitor MOS transistor is thinner than that of the MOS transistor constituting the memory cell to realize a boosted potential generation circuit which has a small area and a large capacity. In this case, preferably, the gate insulating film of the transfer MOS transistor has a thickness which is not greater than that of the gate insulating film of the capacitor MOS transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.