Dynamic random access memory with smart refresh scheduler
US6954387B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 15, 2003 |
| Grant date | Oct 11, 2005 |
| Priority date | — |
| Expiry date | Feb 25, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/104
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a DRAM, which includes a plurality of memory banks, there is a pair of separate flag bit registers for each bank with the flag bit registers that are shifted up/down respectively. A comparator for each bank provides a comparator output. An arbiter for each bank is connected to receive a flag bit up signal and a flag bit down signal from the flag bit registers for that bank and the comparator output from the comparator for that bank. The arbiters are connected to receive a conflict in signal and to provide a conflict out signal. The pair of flag bit registers represent a refresh status of each bank and designate memory banks or arrays that are ready for a refresh operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.