Column repair circuit
US6954399B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 18, 2003 |
| Grant date | Oct 11, 2005 |
| Priority date | — |
| Expiry date | Mar 31, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/812
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A column repair circuit of a semiconductor memory device including a plurality of memory cell array blocks each having the different number of wordlines comprises a predecoder, a block selector, a unit selector and a fuse means. The predecoder decodes a row address. The block selector generates block selecting signals to select the memory cell array blocks. The unit selector generates unit selecting signals to select a size of a row corresponding to the selected memory cell array. The fuse means generates a column repair control signal activated when a column repair is performed on the selected memory cell array block. The column repair circuit performs a column repair operation by a memory cell array block unit, thereby improving column repair efficiency and reducing the number of column repair fuses.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.