Techniques to map cache data to memory arrays
US6954822B2 · kind B2 · utility
8Cited by
9References
24Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 2, 2002 |
| Grant date | Oct 11, 2005 |
| Priority date | — |
| Expiry date | Aug 26, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/3042
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and apparatuses for mapping cache contents to memory arrays. In one embodiment, an apparatus includes a processor portion and a cache controller that maps the cache ways to memory banks. In one embodiment, each bank includes data from one cache way. In another embodiment, each bank includes data from each way. In another embodiment, memory array banks contain data corresponding to sequential cache lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.