Implementation of wait-states
US6954873B2 · kind B2 · utility
4Cited by
7References
28Claims
0Family size
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Key dates
| Filing date | Apr 2, 2002 |
| Grant date | Oct 11, 2005 |
| Priority date | — |
| Expiry date | Sep 14, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00247
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An improved implementation of wait-states in an SOC architecture with optimized performance is described. The clock input signal to the processor is modified during wait-states so that the wait signal does not have to be provided within a short setup time. Data integrity is maintained by providing alternative data paths during wait-states.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.