Patent · US Expired

Error detection in dynamic logic circuits

US6954912B2 · kind B2 · utility

5Cited by

2References

28Claims

0Family size

Assignee

FUJITSU LIMITED · JP

Inventors

Pranjal Srivastava · Los Gatos, US
Ajay Naini · San Jose, US
Atul Dhablania · San Jose, US

Key dates

Filing date	May 17, 2002
Grant date	Oct 11, 2005
Priority date	—
Expiry date	Dec 22, 2023

Classification

Technology area (CPC G)Physics
CPC primaryG01R31/318502
WIPO fieldMeasurement
WIPO sectorInstruments

Abstract

Error detection apparatus and methods for dynamic logic are provided. Circuit errors are detected by comparing true and complement signals to ensure they are in fact complementary signals. A pseudocomplement technique is used to implement an adder in which distinct logic cones generate the true and complement carry signals. Other embodiments comprising additional features, such as shared logic cone decomposition, are also provided.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.