Methodology for fixing Qcrit at design timing impact
US6954916B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 30, 2003 |
| Grant date | Oct 11, 2005 |
| Priority date | — |
| Expiry date | Jul 23, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/33
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and system for simulating an integrated circuit. The method includes the steps of performing a timing analysis of the circuits to ensure that they meet specified timing criteria, performing soft error analysis of the circuits to determine whether they meet specified soft error criteria, and improving those circuits that fail the soft error analysis to improve their resistance to soft errors and having no degradation on timing. Preferably, the improving step includes the step of improving those circuits that fail the soft error analysis by either having an additional voltage source or altering the capacitance of the circuits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.