Manufacturing methods for semiconductor devices with multiple III-V material layers
US6955719B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 18, 2003 |
| Grant date | Oct 18, 2005 |
| Priority date | — |
| Expiry date | Oct 25, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/02631
- WIPO fieldSurface technology, coating
- WIPO sectorChemistry
Abstract
A method for fabricating semiconductor devices with thin (e.g., submicron) and/or thick (e.g., between 1 micron and 100 microns thick) Group III nitride layers during a single epitaxial run is provided, the layers exhibiting sharp layer-to-layer interfaces. According to one aspect, an HVPE reactor is provided that includes one or more gas inlet tubes adjacent to the growth zone, thus allowing fine control of the delivery of reactive gases to the substrate surface. According to another aspect, an HVPE reactor is provided that includes at least one growth zone as well as a growth interruption zone. According to another aspect, an HVPE reactor is provided that includes extended growth sources such as slow growth rate gallium source with a reduced gallium surface area. According to another aspect, an HVPE reactor is provided that includes multiple sources of the same material, for example Mg, which can be used sequentially to prolong a growth cycle.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.