Underfill for maximum flip chip package reliability
US6956165B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 28, 2004 |
| Grant date | Oct 18, 2005 |
| Priority date | — |
| Expiry date | Jun 28, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3511
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An electronic package is disclosed with an underfill with multiple areas of different stiffness and a method of constructing same. An underfill shell region that contacts the chip and the substrate is stiffer than an underfill build region that does not contact either the chip or the substrate. The variation in stiffness may be achieved using materials in the shell that include more filler and/or less solvents than the materials in the bulk region. The underfill may also be composed of a single material with an adhesion to the chip and substrate that is stronger than the material's internal cohesion (e.g., a long chain polymer with an active carboxyl group at the end of the chain). This can be achieved by exposing the chip and substrate surfaces to a curing substance (e.g., vaporized hydrofluoric acid).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.