Delay locked loop device
US6956418B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 31, 2003 |
| Grant date | Oct 18, 2005 |
| Priority date | — |
| Expiry date | Dec 31, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/087
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A delay locked loop device includes a first delay line for receiving an external clock signal and a first delay control signal to generate a first internal clock signal; a second delay line for receiving the external clock signal and a second delay control signal or the first delay control signal to generate a second internal clock signal; a first delay control block for receiving the external clock signal to generate the first delay control signal; a second delay control block for receiving the external clock signal to generate the second delay control signal; and a phase detecting block for receiving the first internal clock signal and the second internal clock signal to generate the on-off signal by comparing a phase of the first internal clock signal with a phase of the second internal clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.