Semiconductor memory device
US6957378B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 3, 2002 |
| Grant date | Oct 18, 2005 |
| Priority date | — |
| Expiry date | Jul 3, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4078
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device is disclosed which comprises a cell array including a normal data section used for normal data write and read and a parity data section used for check data write and read, the check data being for execution of error check of data as read out of the normal data section, a data buffer for temporal stage of read data from the cell array and write data into the cell array, and an ECC circuit for generating the check data to be stored in the parity data section from write data as input during data writing, and for performing error check and correction of data read out of the normal section based on the data read out of the normal data section and the check data read out of said parity data section during data reading. N-bit parallel data transfer is performed between the data buffer and normal data section whereas m-bit parallel data transfer is done between the data buffer and external input/output terminals (where m and n are integers satisfying m<n).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.