Techniques for identifying functional blocks in a design that match a template and combining the functional blocks into fewer programmable circuit elements
US6957412B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 15, 2002 |
| Grant date | Oct 18, 2005 |
| Priority date | — |
| Expiry date | Oct 23, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/34
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Techniques are provided that combine functional blocks in a user design into fewer programmable circuit elements. Systems and methods of the present invention can combine functional blocks in a user design into a single programmable circuit element. A plurality of functional blocks in a user design that can be combined are identified. The possible combinations of functional blocks can be sorted according to a gain function. The gain function can, for example, weigh routing delays caused by a combination. The most desirable combination is selected from the sorted list of possible combinations. The selected combination is checked to see if it is feasible in light of electrical and user-specified constraints. If the combination is feasible, the combination is performed. Combinations continue to be performed by selecting the most desirable combinations from the sorted list.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.