Method of inlining a VHDL function call into Verilog
US6957423B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | May 15, 2001 |
| Grant date | Oct 18, 2005 |
| Priority date | — |
| Expiry date | Oct 27, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F8/51
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of inlining a function call of a first high level design language (HDL) into a second HDL is disclosed comprising the steps of: (a) translating the function call of the first HDL into a function body file of the second HDL; (b) translating a signature of the function call of the first HDL into a data file including predetermined data of the function signature; and (c) translating the function call of the first HDL into a sequence of macro definitions based on the corresponding data file followed by a compiler directive to include the corresponding function body file of the second HDL. In one embodiment, the first HDL is a VHDL and the second HDL is a Verilog HDL.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.