Semiconductor device and manufacturing method thereof
US6958288B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | May 26, 2004 |
| Grant date | Oct 25, 2005 |
| Priority date | — |
| Expiry date | May 26, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/30105
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In a semiconductor device manufacturing process using a low-dielectric-constant insulation film as an interlayer insulation film, a stress exerted on wiring layers and interlayer insulation films is reduced. In a semiconductor device in which a plurality of buried wiring layers are formed in the interlayer insulation films each formed of a low-dielectric-constant insulation film lower in mechanical strength than a silicone oxide film formed by, for example, a CVD method, a first layer of wiring, on a lower layer of which a low-dielectric-constant insulation film is not disposed, serves as a bonding pad, and bump electrodes are formed on the wiring so as to become higher than a position where the uppermost buried wiring is formed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.