Integrated semiconductor product comprising a metal-insulator-metal capacitor

US6958509B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Heinrich Körner · Bogen, DE
• Michael Schrenk · Dießen am Ammersee, DE
• Markus Schwerd · Holzkirchen, DE

Key dates

• Filing date: Jun 10, 2004
• Grant date: Oct 25, 2005
• Expiry date: Jun 10, 2024

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D1/696
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

To fabricate an integrated semiconductor product with integrated metal-insulator-metal capacitor, first of all a dielectric protective layer (5) and a dielectric auxiliary layer (16) are deposited on a first electrode (2). The protective layer and the auxiliary layer (16) are then opened up (17) via the first electrode. Then, a dielectric layer (6) is produced, and the metal track stack (7, 8, 9) for the second electrode is then applied to the dielectric layer (6). This is followed by the patterning of the metal-insulator-metal capacitor using known etching processes. This makes it possible to produce dielectric capacitor layers of any desired thickness using materials which can be selected as desired. In particular, this has the advantage that via etches can be carried out significantly more easily than in the prior art, since it is not necessary to etch through the residual dielectric capacitor layer above the metal tracks.