Floating-gate memory cell having trench structure with ballistic-charge injector, and the array of memory cells

US6958513B2 · kind B2 · utility

Inventor

• Chih-Hsin Wang · San Jose, US

Key dates

• Filing date: Jun 6, 2003
• Grant date: Oct 25, 2005
• Expiry date: Aug 26, 2023

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/6894

Abstract

A method of forming an array of floating gate memory cells, and an array formed thereby, wherein each memory cell includes an electrical conductive floating gate formed in a trench in a semiconductor substrate, and an electrical conductive control gate having a portion disposed over and insulated from the floating gate. An electrical conductive tunneling gate is disposed over and insulated from the control gate by an insulating layer to form a tri-layer structure permitting both electron and hole charges tunneling through at similar tunneling rate. Spaced apart source and drain regions are formed with the source region disposed adjacent to and insulated from a lower portion of the floating gate, and with the drain region disposed adjacent to and insulated from an upper portion of the floating gate with a channel region formed therebetween and along a sidewall of the trench.