Chih-Hsin Wang
57Patents
13h-index
17Co-inventors
77Inventor score
Filing activity: Jul 26, 2001 → Dec 28, 2016
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6756633B2 | Semiconductor memory array of floating gate memory cells with horizontally oriented floating gate edges | Electricity | 296 | Expired |
| US6882572B2 | Method of operating a semiconductor memory array of floating gate memory cells with horizontally oriented edges | Electricity | 266 | Expired |
| US7115942B2 | Method and apparatus for nonvolatile memory | Physics | 74 | Expired |
| US6958513B2 | Floating-gate memory cell having trench structure with ballistic-charge injector, and the array of memory cells | Electricity | 54 | Expired |
| US6541324B1 | Method of forming a semiconductor array of floating gate memory cells having strap regions and a peripheral logic device region | Electricity | 54 | Expired |
| US6861698B2 | Array of floating gate memory cells having strap regions and a peripheral logic device region | Electricity | 22 | Expired |
| US6580642B1 | Method of erasing nonvolatile tunneling injector memory cell | Physics | 22 | Expired |
| US6855980B2 | Semiconductor memory array of floating gate memory cells with low resistance source regions and high source coupling | Electricity | 21 | Expired |
| US6727545B2 | Semiconductor memory array of floating gate memory cells with low resistance source regions and high source coupling | Electricity | 20 | Expired |
| US7257033B2 | Inverter non-volatile memory cell and array system | Physics | 18 | Expired |
| US7015102B2 | Method of forming floating-gate memory cell having trench structure with ballistic-charge injector, and the array of memory cells made thereby | Electricity | 16 | Expired |
| US7375398B2 | High voltage FET gate structure | Electricity | 16 | Expired |
| US7626864B2 | Electrically alterable non-volatile memory cells and arrays | Physics | 15 | Active |
| US6743674B2 | Method of forming a semiconductor array of floating gate memory cells and strap regions, and a memory array and strap regions made thereby | Electricity | 13 | Expired |
| US6627946B2 | Semiconductor memory array of floating gate memory cells with control gates protruding portions | Electricity | 13 | Expired |
| US7107941B2 | Safety device of collar for pet | Human Necessities | 13 | Expired |
| US7180125B2 | P-channel electrically alterable non-volatile memory cell | Electricity | 13 | Expired |
| US7948810B1 | Positive and negative voltage level shifter circuit | Electricity | 13 | Active |
| US7074672B2 | Self aligned method of forming a semiconductor memory array of floating gate memory cells with buried bit-line and vertical word line transistor | Electricity | 12 | Expired |
| US7847374B1 | Non-volatile memory cell array and logic | Electricity | 11 | Active |
| US6952033B2 | Semiconductor memory array of floating gate memory cells with buried bit-line and raised source line | Physics | 11 | Expired |
| US8248848B1 | System and methods for multi-level nonvolatile memory read, program and erase | Physics | 10 | Active |
| US7607586B2 | Semiconductor structure with RF element | Electricity | 10 | Active |
| US8264039B2 | High-voltage LDMOSFET and applications therefor in standard CMOS | Electricity | 9 | Active |
| US7297634B2 | Method and apparatus for semiconductor device and semiconductor memory device | Physics | 8 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.