N-channel LDMOS with buried p-type region to prevent parasitic bipolar effects
US6958515B2 · kind B2 · utility
63Cited by
4References
8Claims
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Key dates
| Filing date | Dec 31, 2001 |
| Grant date | Oct 25, 2005 |
| Priority date | — |
| Expiry date | May 5, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/62
Abstract
An improved n-channel integrated lateral DMOS (10) in which a buried body region (30), beneath and self-aligned to the source (18) and normal body diffusions, provides a low impedance path for holes emitted at the drain region (16). This greatly reduces secondary electron generation, and accordingly reduces the gain of the parasitic PNP bipolar device. The reduced regeneration in turn raises the critical field value, and hence the safe operating area.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.