Low gate resistance layout procedure for RF transistor devices
US6958541B2 · kind B2 · utility
5Cited by
5References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 25, 2003 |
| Grant date | Oct 25, 2005 |
| Priority date | — |
| Expiry date | Jul 25, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A region on a substrate contains multiple transistors in parallel that share a single salicided polysilicon gate electrode. Above or below the gate electrode are formed multiple plugs of refractory material along the length of the gate electrode. The multiple plugs of refractory material electrically interconnect the gate signal line and the salicided polysilicon gate electrode. The plug material is selected to minimize the work function between it and the salicided polysilicon gate electrode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.