Norman Mause
3Patents
3h-index
7Co-inventors
36Inventor score
Filing activity: Jul 25, 2003 → Dec 7, 2004
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6958541B2 | Low gate resistance layout procedure for RF transistor devices | Electricity | 5 | Expired |
| US7082589B2 | Method of generating a schematic driven layout for a hierarchical integrated circuit design | Physics | 5 | Expired |
| US7424690B2 | Interconnect integrity verification | Physics | 3 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.