Cost-effective scan architecture and a test application scheme for scan testing with non-scan test power and test application cost
US6959426B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 19, 2003 |
| Grant date | Oct 25, 2005 |
| Priority date | — |
| Expiry date | Dec 19, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/30
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method and apparatus for scan design architecture with non-scan testing cost is disclosed. In one embodiment, the method comprises: transforming a plurality of sequential cells for a sequential circuit to a plurality of controllable and observable cells for a combinational circuit; connecting said plurality of sequential cells with at least one shifter registers; obtaining at least one scan chains; and substituting the ATPG step for said sequential circuit with the ATPG for said combinational circuit. In another embodiment, the apparatus comprises: means for transforming a plurality of sequential cells for a sequential circuit to a plurality of controllable and observable cells for a combinational circuit; means for connecting said plurality of sequential cells with at least one shifter registers; means for obtaining at least one scan chains; and means for substituting the ATPG step for said sequential circuit with the ATPG for said combinational circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.