Semiconductor package and method of manufacturing the same
US6960494B2 · kind B2 · utility
1Cited by
5References
5Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 21, 2004 |
| Grant date | Nov 1, 2005 |
| Priority date | — |
| Expiry date | Oct 21, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package has (a) a package base, (b) package terminals formed on the package base and used to connect the semiconductor package to another device, (c) a wiring layer formed on the package base and electrically connected to the package terminals, (d) a semiconductor chip mounted on the package base and electrically connected to the wiring layer, (e) a low-elasticity resin layer formed between a resin mold and the wiring layer and between the package base and the resin mold, and (f) the resin mold sealing the package base, the wiring layer, the semiconductor chip, and the low-elasticity resin layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.