Cache coherency mechanism using arbitration masks
US6961825B2 · kind B2 · utility
4Cited by
13References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 24, 2001 |
| Grant date | Nov 1, 2005 |
| Priority date | — |
| Expiry date | Oct 7, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L69/329
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A distributed processing system includes a cache coherency mechanism that essentially encodes network routing information into sectored presence bits. The mechanism organizes the sectored presence bits as one or more arbitration masks that system switches decode and use directly to route invalidate messages through one or more higher levels of the system. The lower level or levels of the system use local routing mechanisms, such as local directories, to direct the invalidate messages to the individual processors that are holding the data of interest.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.